1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a design automation system that automates design of a semiconductor integrated circuit.
2. Description of the Related Art
To test whether or not a semiconductor integrated circuit (hereafter referred to as “LSI”) has been manufactured normally, a scan test method is generally used. A scan test is executed by substituting flip-flops (for convenience, “flip-flop” is hereafter referred to as “F/F”) within an LSI by F/Fs having input/output terminals for a scan test called scan F/Fs. A plurality of such scan F/Fs are connected in series to form a scan chain structure within the LSI and a test pattern is inputted directly to the scan F/Fs from external terminals of the LSI. Moreover, data of the scan F/Fs is outputted directly to the external terminals of the LSI.
An LSI designed to enable execution of this kind of scan test can be treated as a combinational circuit even though it is a sequential circuit including scan F/Fs. Therefore, it is possible to automatically generate a test pattern by way of an ATPG (Automatic Test Pattern Generation) tool.
Generally, in a scan shift operation in the scan test, all of the F/Fs are directly controlled by a clock that is inputted from external terminals. To execute the scan shift operation without any faulty input or misreading of data, it is necessary that the clock of the serially connected F/Fs rises simultaneously. Even if an internally inverted clock is provided to the clock terminals of the scan F/F or an inverted edge scan F/F exists, it is possible to correctly execute a shift operation provided that those scan F/Fs are positioned at the head of the scan chain.
This scan design enables the LSI testing to be performed easily. However, during the scan test, all of the scan F/Fs operate simultaneously, and the circuit is brought into a highly activated state because the internal state thereof changes frequently. Therefore, power consumption may become a problem (see, for example, P. Girad, “Survey of Low-Power Testing of VLSI Circuits,” IEEE Design & Test of Computers, Vol. 19, No. 3, pp. 82-92, 2002). In general, clock gating design is applied in an LSI modified for low power consumption, power consumption is restrained by stopping a clock supply to an F/F that is not in operation (whose output value does not change).
Power consumption in question can be broadly divided into two categories of instantaneous power (peak power) that is consumed instantaneously and average power that is consumed on average for a certain fixed period. In a scan shift in which all scan F/Fs operate at the same time, an average power can be restrained by creating a test pattern with a small number of toggles as far as possible. However, since all the scan F/Fs operate simultaneously, this is an insufficient countermeasure in restraining instantaneous power. By dividing up the scan chain by clock domain and executing the scan shift with delays in the clock, it is possible to perform a normal scan shift without faulty input or misreading of data while reducing instantaneous power. However, in the case that there exists a main clock domain extending over the entire LSI, there is a problem that, because the majority of F/Fs within that domain operate simultaneously, the effect of reducing power consumption is small. It is possible to divide a main clock domain into a plurality of clock domains at the time of test only, and apply a plurality of external clocks, but there is a problem that this increases the burden of clock design.